A symmetric multiprocessing (SMP) architecture generally is a multiprocessor computer architecture where two or more identical processors can connect to a single shared main memory. In the case of multi-core processors, the SMP architecture can apply to the CPU cores.
In an SMP architecture, multiple networking CPUs or CPU cores can receive and transmit network traffic. Generally, multiple CPU cores are fastpath processors that perform “fast” network processing operations. The fastpath processors do not block themselves and wait for other components or modules during the processing of network packets. Whenever an exception occurs in a fastpath CPU processor, the exception is passed onto a slowpath processor for further handling in order to ensure the processing speed of the fastpath processors. Moreover, whenever an exception occurs in a slowpath CPU processor, the exception is typically passed onto control plane processor for further handling.
On a highly scalable platform, it is possible that a large volume of exceptions get passed from fastpath processors to the slowpath processor, and further to the control plane processor. This may lead to a number of problems. First, the control plane processor may slow down its processing speed when it is burdened with a large volume of exception handlings, which may eventually lead to non-convergence of the operations. Specifically, when the control plane processor slows down at processing the exceptions, more exceptions will be accepted into the processing queue. Then, more and more of the accepted exceptions will not be able to get processed before they time out. Thus, the same request would need to be started over again from the fastpath processors.
Second, because the operations take longer in the scenario where there are a large volume of exceptions that need to be handled by the system, redundant exceptions may occur for the same use case. For example, assuming that an exception occurred due to a user miss (for example, when there is no corresponding authenticated user entry recognized by the system) while processing a layer 3 (L3) packet, the layer 3 packet will be passed to control plane for further processing, e.g., to trigger a user authentication operation. The user authentication operation from the control plane processor may require sending a retry authentication request packet. Normally, when the user is authenticated as a result of successful user authentication operation, a user entry may be cached by the system in a shared memory. Thus, subsequent L3 packets would not encounter the same user miss.
Nevertheless, as the volume of exceptions increase, because the system takes a longer processing time with higher volume, the control plane processor may need to send multiple retry authentication requests for the same L3 packet. These multiple retry authentication requests will create exactly the same exceptions at the fastpath processors, which will be passed on to slowpath processor and further to the control plane processor, because the system had not successfully completed the user authentication operation and cached the corresponding user entry. Thus, the longer it takes for the control plane processor to complete an operation, the more likely for the control plane processor to receive the same exceptions over and over due to prior delayed or unsuccessful completion of the corresponding operation. Thus, the slow processing time with a high volume of exception handling requests is exacerbated by the additional load of the same exceptions generated from retry packets because of the initial slow processing time.